The present inventive subject matter relates to the electronic arts. It finds particular application in conjunction with group III-V flip-chip bonded light emitting diodes (LEDs) for lighting applications, and will be described with particular reference thereto. However, one of ordinary skill in the art will appreciate that it is also amenable to other like applications, e.g., in conjunction with, other types of flip-chip LEDs, other flip-chip bonded epitaxial semiconductor devices (such as vertical cavity surface emitting laser diodes), other non-flip-chip bonding arrangements, etc.
Traditionally, LEDs have been packaged with a die or chip having its substrate down on a heat sink; here, light is extracted from the LED through current spreading, semi-transparent layers deposited on, for example, the die or chip's p-type layer. However, the overall light extraction efficiency of the device can be hindered due to light absorption in the current spreading layer. An alternative method to the aforementioned packaging is to use a flip-chip geometry in which light extraction is primarily through the substrate. For example, it has been shown that a 60% increase in light extraction efficiency can be obtained by flip-chip mounting.
The manufacture of a high lumen output LED can benefit from flip-chip packaging or mounting. In the flip-chip mounting configuration, an LED die (typically, with a light-transmissive substrate arranged on a back side and p and n-electrodes arranged on a front side opposite the back side) is bonded “face down” to a mount or sub-mount, i.e., with the epitaxial layers proximate to the mount and the substrate distal from the mount. The flip-chip arrangement has a number of advantages, e.g., including improved thermal heat sinking due to the proximity of the active layers to the heat sink, and reduction of electrode shadowing losses.
In flip-chip mounting configurations, solder bumps (e.g., greater than approximately 50 μm) are typically used to attach the die or chip to its mount or sub-mount (see, e.g., FIG. 1). FIG. 1 shows an LED including a die or chip 10 attached or being attached to a support 20 via solder bumps 30. The die 10 has an epitaxial structure 12, typically including multiple layers of semiconductor material and forming an active light-generating region 14 (e.g., a double heterostructure, multiple quantum well (MQW), or other suitable light-generating configuration), that is usually disposed on a substrate 16 that is substantially transparent or transmissive to light at the wavelength generated. A pair of electrodes and/or electrical contacts (e.g., a p-type contact 18p and an n-type contact 18n) are also arranged on the LED in operative electrical communication with the light-generating region 14 so that electrical power supplied to the LED therethrough drives the same to generate light. In a so called lateral current flip-chip LED device, the electrodes are commonly located on the same side of the epitaxial structure 12 generally opposite the substrate 16, as opposed to a so called vertical current LED device where the pair of electrodes are usually arranged on two sides of the LED, each on a side opposite from the other.
In operation, an electric current passed through the LED, using the electrical contacts, is carried principally by electrons in an n-type layer 12n and by electron vacancies or “holes” in a p-type layer 12p. The electrons and holes move in opposite directions toward the active region 14 or a junction, where they recombine with one another. Energy released by the electron-hole recombination is emitted from the LED as light. As used herein, the term “light” includes visible light as well as electromagnetic radiation in the infrared and ultraviolet wavelength ranges. The wavelength of the emitted light depends upon many factors, including the composition of the semiconductor materials, the structure of the junction, the presence or absence of impurities or doping, and the like.
Commonly, the LED is mounted to the support 20 (e.g., a sub-mount, printed circuit board (PCB), reflector cup, etc.) in flipped orientation, that is, with the light-generating region 14 proximate to the support 20 and the substrate 16 distal from the support 20. In the flip chip arrangement, the goal is generally to extract a substantial amount of light from the LED through the light-transmissive substrate 16.
FIG. 2 shows a typical contact layout or contact trace for flip-chip bonding. Bump areas, are designated for each electrode or contact type. For example, n-type bump areas 32n are designated on the n-type contact 18n, and p-type bump areas 32p are designated on the p-type contact 18p. The respective bump areas correspond to the locations, within the respective p and n-type contact layouts or traces, where the solder bumps 30 contact and/or bond with the respective p and n-type electrodes or contacts 18p and 18n. 
For flip-chip packaging of LEDs, solder attachment has its own merits and drawbacks. One advantage is that the relatively large thickness of the solder tends to planarize; thus, limiting restrictions that are placed on the difference in thickness between, or the relative elevation/height of, the p and n-type contacts 18p and 18n. Note, e.g., the different elevations of the p and n-type contacts 18p and 18n in FIG. 1. Solder attachment of the chip 10 to the support 20, however, can suffer from high thermal resistance; in addition, since it is often the first step of a packaging process, a high re-flow temperature can be demanded (e.g., greater than approximately 250° C.) and this may compromise the reflectivity of the p-type contact 18p, which is otherwise desirable. Also, solder processes typically require cleaning of flux residue after bonding. The cleaning solution or residual flux may compromise the LED's reliability by creating a leakage path through resistive shunt.
In a flip-chip LED configuration, desirable characteristics for die attachment include low thermal resistivity and structural robustness. Both of these can be fulfilled by using thermosonic (TS) bonding for packaging or mounting. However, the TS bonding process can present its own challenges, e.g., maintaining good contact across the chip area.
With reference to FIG. 3, TS bonding typically employs Au bumps 34 arranged on the support 20 that enable the chip or die 10 (via the p and n-type contacts 18p and 18n which are also typically terminated with Au) to be attached or bonded to the support 20 with the application of ultrasonic energy, and without any intermediate melting/re-solidification step. Consequently, lower packaging temperatures (e.g., around approximately 150° C.) can be used, thus avoiding loss of reflectivity of the p-type contact 18p. In addition, the use of Au bumps 34 instead of solder, lowers the thermal resistance of the package.
Commonly, deformation of the Au bumps 34, and physical bonding of the Au bumps 34 to the respective p and n-type bump areas 32p and 32n designated on the chip 10, occurs in TS bonding. Accordingly, it is advantageous to have the p and n-type bump areas 32p and 32n on the chip 10 at more or less the same elevation, i.e., within the extent of deformation of the Au bumps 34. The tendency is therefore to manufacture an LED die for use in a TS bonding application with a thickened or elevated n-type contact 18n. Note, e.g., the substantially similar elevations of the p and n-type contacts 18p and 18n in FIG. 3, and compare the thickness or elevation of the n-type contact 18n in FIG. 3 with that of FIG. 1.
In a typical chip 10, a significant amount of the light may be emitted from a outer periphery of the active region 14. However, as can be appreciated, with a contact layout or trace such as that illustrated in FIG. 2 and contact elevations such as those illustrated in FIG. 3, the n-type contact 18n completely encircles the outer periphery of the active region 14. Consequently, light emitted therefrom may be blocked from exiting the die 10, e.g., getting absorbed, or otherwise trapped in the die 10, by the n-type contact layout or trace on the chip 10. This can result in a significant loss of light extraction efficiency.
At first glance, it might appear from FIGS. 1 through 3, that the easiest way to minimize the aforementioned light extraction issue is to eliminate that portion of the n-type contact layout or trace not containing any n-type bump areas 32n, e.g., having a contact layout or trace as shown in FIG. 4, where the n-type contact 18n is restricted to one edge of the die 10, or so that the n-type trace does not encircle the entire outer periphery. However, this can lead to poor current spreading and non-uniform light emission. For example, most of the light would tend to be emitted from that portion of the active region 14 where the p-type layer 12p is proximate to the n-type trace or contact 18n, which would in turn still hinder its extraction.
In some designs, the n-type trace can include several electrically separated regions or pieces, interconnected only on the mount or sub-mount level. However, if the chip or mount or sub-mount planarity is imperfect, one of such pieces may not be firmly connected to the bumps, resulting in higher electrical resistance of that piece and current spreading non-uniformity.
Accordingly, a new and improved LED and/or semiconductor die and/or method for packaging and/or mounting the same is disclosed that overcomes the above-referenced problems and others.